Specifications

Index
Index-5
QEP decoding 6-79
QEP circuit 6-79
QEP decoding example 6-80
QEP pins 6-78
quadrature encoder pulse (QEP) circuit 6-78
register addresses 6-11, 6-13
register setup for PWM generation 6-56
register setup for QEP circuits 6-80
registers 6-9
space vector PWM 6-60
3–phase power inverter 6-60
approximating motor voltage with basic space
vectors 6-62
power inverter switching patterns and basic
space vectors 6-60
space vector PWM boundary conditions 6-64
space vector PWM waveform generation with
event manager 6-62
hardware 6-63
software 6-63
space vector PWM waveforms 6-64
unused compare register 6-64
symmetric PWM waveform generation 6-58
timer control registers (TxCON and
GPTCON) 6-31
individual GP timer control register
(TxCON) 6-31
overall GP timer control register
(GPTCON) 6-33
EVIFRA, EV2 interrupt flag register A 6-85
EVIFRB, EV2 interrupt flag register B 6-87
EVIFRC, EV2 interrupt flag register C 6-88
EVIMRA, EV2 interrupt mask register A 6-89
EVIMRB, EV2 interrupt mask register B 6-90
EVIMRC, EV2 interrupt mask register C 6-90
examples of ’24x program code B-1 to B-42
external interrupt control registers 2-36
external interrupts 4-4
external memory interface (XMIF)
I/O space 3-20
program space 3-20
wait–state generator 3-21
’C24x wait–state generator control register
(WSGR) 3-22
generating wait states with the ’C243 wait-
state generator 3-21
generating wait–states with the READY sig-
nal 3-21
setting the number of wait states with the
’F243 WSGR bits 3-23
XMIF qualifier signal description 3-17
program address data – visibility functional
timing 3-18, 3-19
XMIF signal descriptions 3-17
F
factory masked on–chip ROM 3-2
flash 3-2
flash control register access 3-2
G
generating executable files, figure B-2
global data memory 3-15
address generation 3-16
configuration 3-15
global memory allocation register (GREG) 3-15
global memory allocation register (GREG) 3-15
glossary D-1
GREG 3-15
GSR (global status register), figure 10-28
I
I/O mux control register A, configuration 5-6
I/O mux control register A (OCRA) 5-5
I/O mux control register B (OCRB) 5-6
I/O MUX control registers 5-5
IFR 2-23 to 2-38
illegal address detect 2-35
IMR 2-25 to 2-38
instruction register (IR), definition D-7
interrupt
definitions D-7
hierarchy 2-14
latency 2-21
nonmaskable 2-18
operation sequence 2-19
peripheral interrupt acknowledge descriptions
(PIACKR0) 2-32
interrupt
peripheral interrupt acknowledge descriptions
(PIACKR1) 2-33