Specifications

Index
Index-4
capture FIFO status register
(CAPFIFO) 6-73
capture units, features 6-68
compare unit interrupts 6-45
compare unit registers 6-39
compare action control register (ACTR) 6-42
compare control register (COMCON) 6-39
compare unit reset 6-45
compare units 6-37
compare inputs/outputs 6-38
compare operation modes 6-38
operation 6-38
register setup for compare unit opera-
tion 6-39
comparison to ’C240 EV 6-5
EV2 interrupt flag registers 6-85
EV2 interrupt flag register A 6-85
EV2 interrupt flag register B 6-87
EV2 interrupt flag register C (EVIFRC) 6-88
EV2 interrupt mask registers 6-89
EV2 interrupt mask register A
(EVIMRA) 6-89
EV2 interrupt mask register B 6-90
EV2 interrupt mask register C
(EVIMRC) 6-90
EV2 interrupt request and service 6-82
interrupt generation 6-84
interrupt vector 6-85
EV2 interrupts 6-9, 6-82
functional blocks 6-2
general purpose (GP) timers 6-14
double buffering of GP timer compare and
period registers 6-17
GP timer block diagram 6-15
GP timer compare output 6-18
GP timer compare registers 6-17
GP timer inputs 6-15
GP timer interrupts 6-20
GP timer outputs 6-16
GP timer period register 6-17
GP timer synchronization 6-19
GP timr in emulation suspend 6-20
individual GP timer control register
(TxCON) 6-16
overall GP timer control register
(GPTCON) 6-16
QEP based clock input 6-19
starting the A/D converter with a timer
event 6-20
timer clock 6-18
timer counting direction 6-18
timer functional blocks 6-14
generation of PWM outputs using GP
timers 6-35
PWM operation 6-36
generation of PWM outputs with event manag-
er 6-56
asymmetric and symmetric PWM genera-
tion 6-56
GP timer compare operation 6-26
active/inactive time calculation 6-30
asymmetric waveform generation 6-26
asymmetric/symmetric waveform genera-
tor 6-26
Compare/PWM transition 6-26
output logic 6-29
symmetric waveform generation 6-27
GP timer counting operation 6-21
continuous–up counting mode 6-21
continuous–up/down counting mode 6-24
directional–up/down counting mode 6-23
stop/hold mode 6-21
GP timer reset 6-36
operation of capture units 6-69
capture unit setup 6-70
capture unit time base selection 6-69
output logic 6-53
output logic block diagram 6-54
pins 6-6, 6-7, 6-8
power drive protection 6-8
programmable dead–band unit 6-48
dead–band generation 6-50
dead–band generation examples 6-51
dead–band timer control register
(DBTCON) 6-48
dead–band unit block diagram 6-52
features of dead–band units 6-53
inputs and outputs of dead–band unit 6-50
PWM circuits associated with compare
units 6-46
PWM generation capability of EV 6-47
PWM waveform generation with compare units
and PWM circuits 6-55
dead band 6-55
PWM signal generation 6-55
QEP circuit time base 6-78
QEP circuit block diagram 6-78
QEP counting 6-80
GP timer interrupt and compare outputs in
QEP operation 6-80