Specifications

Index
Index-3
CAN data frame 10-4
CAN error counter register (CEC), figure 10-31
CAN initialization, figure 10-36
CAN interrupt flag register (CAN_IFR),
figure 10-33
CAN interrupt mask register (CAN_IMR),
figure 10-35
CAN notation, table 10-39
power-down mode 10-37
CAN protocol overview 10-3
configuration mode 10-36
control registers 10-18
error status register (ESR), figure 10-29
global status register (GSR), figure 10-28
interrupt logic 10-32
introduction 10-2
local accepance mask (LAM) 10-16
local acceptance mask register n (0,1) high word
(LAMn_H), figure 10-17
local acceptance mask register n (0,1) low word
(LAMn_L), figure 10-17
mailbox addresses 10-8
mailbox configuration details, table 10-5
mailbox direction enable register (MDER),
figure 10-18
mailbox layout 10-10
mailbox RAM 10-10
write access 10-12
mailboxes
receive 10-13
transmit 10-13
master control register (MCR), figure 10-22
memory map 10-6
message buffers 10-12
message control field (MSGCTRLn),
figure 10-11
message identifier 10-10
message identifier for high word mailboxes 0–5
(MSGIDnH), figure 10-10
message identifier for low word mailboxes 0–5
(MSGIDnL) 10-11
message objects 10-9
CAN data frame, figure 10-9
overview of the CAN network 10-3
overwrite protection control (OPCn) 10-22
receive control register (RCR), figure 10-21
receive message lost (RMLn) 10-21
receive message pending (RMPn) 10-22
register addresses, table 10-7
remote frame handling 10-14
remote frame pending register (RFPn) 10-21
remote frame requests, figure 10-16
remote requests
receiving 10-14
sending 10-15
status registers 10-28
suspend mode 10-38
transmission acknowledge (TAn) 10-19
transmission control register (TCR),
figure 10-19
transmission request reset (TRRn) 10-20
transmission request set (TRSn) 10-20
CONV (conversion time) 7-34
CPU, definition D-3
D
D0–D15 (external data bus), definition D-4
data memory
global data memory 3-15
local data memory 3-12
on-chip registers 3-15
data page 0
address map 3-14
on-chip registers 3-14
RAM block B2 (scratch-pad RAM) 3-14
DBTCON, dead–band timer control register 6-48
digital I/O ports module 5-1
digital I/O ports register implementation 5-2
DMC systems 1-3
dual-access RAM (DARAM) D-4
E
enabling, parity 2-24, 2-25, 2-26
EOC (end of conversion cycle) 7-34
EOS (end of sequence flag–setting cycle) 7-34
ESR (error status register), figure 10-29
event manager (EV2) 6-1
asymmetric PWM waveform generation 6-57
block diagram 6-3
capture interrupts 6-77
capture unit FIFO stacks 6-75
first capture 6-76
second capture 6-76
third capture 6-76
capture unit registers 6-70
capture control register (CAPCON) 6-70