Specifications

Index
Index-2
interrupt logic 10-32
introduction 10-2
local acceptance mask (LAM) 10-16
local acceptance mask register n (0,1) high word
(LAMn_H), figure 10-17
local acceptance mask register n (0,1) low word
(LAMn_L), figure 10-17
mailbox addresses 10-8
mailbox configuration details, table 10-5
mailbox direction enable register (MDER),
figure 10-18
mailbox layout 10-10
mailbox RAM 10-10
write access 10-12
mailboxes
receive 10-13
transmit 10-13
master control register (MCR), figure 10-22
memory map 10-6
message buffers 10-12
message control field (MSGCTRLn),
figure 10-11
message identifier 10-10
message identifier for high word mailboxes 0–5
(MSGIDnH), figure 10-10
message identifier for low word mailboxes 0–5
(MSGIDnL), figure 10-11
message objects 10-9
CAN data frame, figure 10-9
overview of the CAN network 10-3
overwrite protection control (OPCn) 10-22
power- down mode 10-37
receive control register (RCR), figure 10-21
receive message lost (RMLn) 10-21
receive message pending (RMPn) 10-22
register addresses, table 10-7
remote frame handling 10-14
remote frame pending register (RFPn) 10-21
remote frame requests, figure 10-16
remote requests
receiving 10-14
sending 10-15
status registers 10-28
suspend mode 10-38
transmission acknowledge (TAn) 10-19
transmission control register (TCR), fig-
ure 10-19
transmission request reset (TRRn) 10-20
transmission request set (TRSn) 10-20
CAN bit timing, figure 10-27
CAN bit timing examples 10-27
CAN configuration mode 10-36
CAN control registers 10-18
CAN initialization 10-36
CAN interrupt logic 10-32
CAN notation 10-39
CAN power-down mode 10-37
CAN status registers 10-28
CAN suspend mode 10-38
CAN_IFR (CAN interrupt flag register),
figure 10-33
CAN_IMR (CAN interrupt mask register),
figure 10-35
CAPCON, capture control unit 6-70
CAPFIFO, capture FIFO status register 6-73
CEC (CAN error counter register), figure 10-31
CHAR LEN2–0 bits 2-24
character length 2-24
CLKOUT1 signal, definition D-3
clock, pins 4-2
clock domains 4-3
clocks 4-1
codec, definition D-3
COMCON, compare control register 6-39
compatibility 12-1
analog–to–digital converter 12-4
event manager 12-3
general 12-2
serial communication interface 12-4
serial peripheral interface 12-4
watchdog timer 12-4
configuration, global data memory 3-15
configuration registers 2-3
control bits
CHAR LEN2–0 2-24
PARITY ENABLE 2-24, 2-25, 2-26
STOP BITS 2-24, 2-25
controller area network (CAN) 10-1
abort acknowledge (AAn) 10-19
acceptance filter 10-16
architecture 10-4
bit configuration register 1 (BCR1), figure 10-25
bit configuration register 2 (BCR2), figure 10-25
bit configuration registers (BCRn) 10-24
bit timing, figure 10-27
block diagram 10-4
CAN bit timing examples, table 10-27