Specifications

Interrupt Vectors
2-16
2.5 Interrupt Vectors
When the CPU receives an interrupt request, it does not know which peripheral
event caused the request. To enable the CPU to distinguish between all of
these events, a unique peripheral interrupt vector is generated in response to
an active peripheral interrupt request. This vector is loaded into the peripheral
interrupt vector register (PIVR) in the PIE controller. It can then be read by the
CPU and used to generate a vector to branch to the interrupt service routine
(ISR) which corresponds to the event being acknowledged.
In effect there are two vector tables: The CPU’s vector table which is used to
get to the first, general interrupt service routine (GISR) in response to a CPU
interrupt request; and the peripheral vector table which is used to get to the
event specific interrupt service routine (SISR) corresponding to the event
which caused the PIRQ. The code in the GISR should read the PIVR, and after
saving any necessary context, use this value to generate a vector to the SISR.
Figure 2–6 shows an example of how XINT1 (external interrupt in high-priority
mode) generates an interrupt. For XINT1 in high-priority mode, a value of
0001h is loaded in the PIVR register. The CPU ascertains what value was
loaded in the PIVR register and uses this value to determine which peripheral
caused the interrupt and then branches to the appropriate SISR. Such a
branch to the SISR could be a conditional branch (BCND) which is executed
on the condition that the PIVR register holds a particular value. An alternative
scheme would be to left-shift the PIVR register by 1 bit while loading it in the
accumulator and adding a fixed offset value. Program control could then
branch to the address value stored in the accumulator (using BACC instruc-
tion). This address would point to the SISR.