Specifications
Index
Index-1
Index
A
AAn (abort acknowledge) 10-19
acceptance filter 10-16
accumulator, definition D-1
ACQ (acquisition time) 7-34
ACTR, compare action control register 6-42
ADC (analog to digital converter)
ADC control register 1 (ADCTRL1) 7-20
ADC control register 2 (ADCTRL2) 7-23
autoconversion sequencer 7-4
autosequence status register
(AUTO_SEQ_SR) 7-29
autosequenced ADC in cascaded mode, block
diagram 7-5
autosequenced ADC with dual-sequencers, block
diagram 7-6
calibration 7-18
clock prescaler 7-16
conversion clock cycles 7-34
conversion result buffer registers, (for dual-se-
quencer mode) 7-33
features 7-2
input channel select sequencing control registers,
(CHSELSEQn) 7-31
input trigger description 7-12
maximum converson channels register
(MAX_CONV) 7-27
overview 7-4
register addresses 7-3
register bit descriptions 7-20
self-test 7-19
single and cascaded operating modes, compari-
son 7-7
address map, local data memory, data page 0 3-14
addressing
bit-reversed indexed D-2
global data memory 3-16
addressing modes, definition D-1
architecture, summary 2-2
auxiliary register pointer (ARP) D-2
auxiliary register pointer buffer (ARB) D-2
B
BCR1 (bit configuration register 1), figure 10-25
BCR2 (bit configuration register 2), figure 10-25
BCRn (bit configuration registers) 10-24
bit-reversed indexed addressing D-2
C
CALU (central arithmetic logic unit), definition D-3
CAN (controller area network) 10-1
abort acknowledge (AAn) 10-19
acceptance filter 10-16
architecture 10-4
bit configuration register 1 (BCR1), figure 10-25
bit configuration register 2 (BCR2), figure 10-25
bit configuration registers (BCRn) 10-24
block diagram 10-4
CAN bit timing examples, table 10-27
CAN bit timing, figure 10-27
CAN data frame, figure 10-4
CAN error counter register (CEC), figure 10-31
CAN initialization, figure 10-36
CAN interrupt flag register (CAN_IFR),
figure 10-33
CAN interrupt mask register (CAN_IMR),
figure 10-35
CAN notation, table 10-39
CAN protocol overview 10-3
configuration mode 10-36
control registers 10-18
error status register (ESR), figure 10-29
global status register (GSR), figure 10-28