Specifications

Glossary
D-12
program control logic: Logic circuitry that decodes instructions, manages
the pipeline, stores status of operations, and decodes conditional
operations.
program counter (PC): A register that indicates the location of the next
instruction to be executed.
program read bus (PRDB): A 16-bit internal bus that carries instruction
code and immediate operands, as well as table information, from
program memory to the CPU.
PS: Program select pin . The ’24x asserts PS to indicate an access to exter-
nal program memory.
PSLWS:
Lower program-space wait-state bits. A value in the wait-state
generator control register (WSGR) that determines the number of wait
states applied to reads from and writes to off-chip lower program space
(addresses 0000h–7FFFh). See also PSUWS .
PSUWS: Upper program-space wait-state bits. A value in the wait-state
generator control register (WSGR) that determines the number of wait
states applied to reads from and writes to off-chip upper program space
(addresses 8000h–FFFFh). See also PSLWS .
R
RD: Read select pin . The ’24x asserts RD to request a read from external
program, data, or I/O space. RD can be connected directly to the output
enable pin of an external device.
READY: External device ready pin . Used to create wait states externally.
When this pin is driven low, the ’24x waits one CPU cycle and then tests
READY again. After READY is driven low, the ’24x does not continue pro-
cessing until READY is driven high.
repeat counter (RPTC): A 16-bit register that counts the number of times
a single instruction is repeated. RPTC is loaded by an RPT instruction.
reset: A way to bring the processor to a known state by setting the registers
and control bits to predetermined values and signaling execution to start
at address 0000h.
reset pin (RS): A pin that causes a reset.
reset vector: The interrupt vector for reset.
return address: The address of the instruction to be executed when the
CPU returns from a subroutine or interrupt service routine.