Specifications

Glossary
D-11 Glossary
PC: See program counter (PC).
PCB: Printed circuit board .
pending interrupt: A maskable interrupt that has been successfully
requested but is awaiting acknowledgement by the CPU.
pipeline: A method of executing instructions in an assembly line fashion.
The ’24x pipeline has four independent phases. During a given CPU
cycle, four different instructions can be active, each at a different stage
of completion. See also instruction-fetch phase ; instruction-decode
phase ; operand-fetch phase; instruction-execute phase .
PLL: Phase lock loop circuit.
PM bits: See product shift mode bits (PM).
power-down mode: The mode in which the processor enters a dormant
state and dissipates considerably less power than during normal opera-
tion. This mode is initiated by the execution of an IDLE instruction. During
a power-down mode, all internal contents are maintained so that opera-
tion continues unaltered when the power-down mode is terminated. The
contents of all on-chip RAM also remains unchanged.
PRDB: See
program read bus (PRDB).
PREG: See product register (PREG).
product register (PREG): A 32-bit register that holds the results of a multi-
ply operation.
product shifter: A 32-bit shifter that performs a 0-, 1-, or 4-bit left shift, or
a 6-bit right shift of the multiplier product based on the value of the
product shift mode bits (PM).
product shift mode: One of four modes (no-shift, shift-left-by-one, shift-left-
by-four, or shift-right-by-six) used by the product shifter.
product shift mode bits (PM): Bits 0 and 1 of status register ST1; they iden-
tify which of four shift modes (no-shift, left-shift-by-one, left-shift-by-four,
or right-shift-by-six) will be used by the product shifter.
program address bus (PAB): A 16-bit internal bus that provides the
addresses for program-memory reads and writes.
program-address generation logic: Logic circuitry that generates the
addresses for program memory reads and writes, and an operand
address in instructions that require two registers to address operands.
This circuitry can generate one address per machine cycle. See also
data-address generation logic.