Specifications

Glossary
D-8
interrupt vector: A branch instruction that leads the CPU to an interrupt
service routine (ISR).
interrupt vector location: An address in program memory where an inter-
rupt vector resides. When an interrupt is acknowledged, the CPU
branches to the interrupt vector location and fetches the interrupt vector.
INTM bit: See interrupt mode bit (INTM) .
I/O-mapped register: One of the on-chip registers mapped to addresses in
I/O (input/output) space. These registers, which include the registers for
the on-chip peripherals, must be accessed with the IN and OUT instruc-
tions. See also memory-mapped register .
IR: See
instruction register (IR).
IS: I/O space select pin . The ’24x asserts IS to indicate an access to external
I/O space.
ISR: See
interrupt service routine (ISR) .
ISWS: I/O-space wait-state bit(s). A value in the wait-state generator control
register (WSGR) that determines the number of wait states applied to
reads from and writes to off-chip I/O space.
L
latch phase: The phase of a CPU cycle during which internal values are held
constant. See also
logic phase ; CLKOUT1 .
logic phase: The phase of a CPU cycle during which internal values are
changed. See also latch phase ; CLKOUT1 .
long-immediate value: A 16-bit constant given as an operand of an
instruction that is using immediate addressing.
LSB:
Least significant bit. The lowest order bit in a word. When used in plural
form (LSBs), refers to a specified number of low-order bits, beginning
with the lowest order bit and counting to the left. For example, the four
LSBs of a 16-bit value are bits 0 through 3. See also
MSB .
M
machine cycle: See CPU cycle .
maskable interrupt: A hardware interrupt that can be enabled or disabled
through software. See also nonmaskable interrupt .