Specifications
Glossary
D-7
Glossary
instruction-decode phase: The second phase of the pipeline; the phase in
which the instruction is decoded. See also
pipeline
;
instruction-fetch
phase
;
operand-fetch phase; instruction-execute phase
.
instruction-execute phase: The fourth phase of the pipeline; the phase in
which the instruction is executed. See also
pipeline
;
instruction-fetch
phase
;
instruction-decode phase
;
operand-fetch phase
.
instruction-fetch phase: The first phase of the pipeline; the phase in which
the instruction is fetched from program-memory. See also
pipeline
;
instruction-decode phase
;
operand-fetch phase; instruction-execute
phase
.
instruction register (IR): A 16-bit register that contains the instruction
being executed.
instruction word: A 16-bit value representing all or half of an instruction. An
instruction that is fully represented by 16 bits uses one instruction word.
An instruction that must be represented by 32 bits uses two instruction
words (the second word is a constant).
internal interrupt: A hardware interrupt caused by an on-chip peripheral.
interrupt: A signal sent to the CPU that (when not masked or disabled)
forces the CPU into a subroutine called an interrupt service routine (ISR).
This signal can be triggered by an external device, an on-chip peripheral,
or an instruction (INTR, NMI, or TRAP).
interrupt flag register (IFR): A 16-bit memory-mapped register that indi-
cates pending interrupts. Read the IFR to identify pending interrupts and
write to the IFR to clear selected interrupts. Writing a 1 to any IFR flag
bit clears that bit to 0.
interrupt latency: The delay between the time an interrupt request is made
and the time it is serviced.
interrupt mask register (IMR): A 16-bit memory-mapped register used to
mask external and internal interrupts. Writing a 1 to any IMR bit position
enables the corresponding interrupt (when INTM = 0).
interrupt mode bit (INTM): Bit 9 in status register ST0; either enables all
maskable interrupts that are not masked by the IMR or disables all mask-
able interrupts.
interrupt service routine (ISR): A module of code that is executed in
response to a hardware or software interrupt.
interrupt trap: See
interrupt service routine (ISR)
.