Specifications

Peripheral Interrupt Expansion (PIE)
2-15 System Configuration and Interrupts
2.4.3 Interrupt Acknowledge
The hierarchical interrupt expansion scheme requires one interrupt acknowl-
edge signal for each peripheral interrupt request to the interrupt controller.
When the CPU asserts its interrupt acknowledge, it simultaneously puts a val-
ue on the program address bus, which corresponds to the CPU interrupt being
acknowledged. (It does this to fetch the interrupt vector from program memory:
each INTn has a vector stored in a dedicated program memory address.) This
value is shown in Table 2–2,
’240x Interrupt Source Priority and Vectors , on
page 2-8. The PIE controller decodes this value to determine which of the
CPU interrupt requests is being acknowledged. It then generates a peripheral
interrupt acknowledge in response to the highest priority, currently asserted
PIRQ associated with that CPU interrupt.