Specifications

Peripheral Interrupt Expansion (PIE)
2-14
2.4.1 Interrupt Hierarchy
The number of interrupt slots available is expanded by having two levels of
hierarchy in the interrupt request system. Both the interrupt request/acknowl-
edge hardware and the interrupt service routine software have two levels of
hierarchy.
2.4.2 Interrupt Request Structure
At the lower level of the hierarchy, the peripheral interrupt requests (PIRQ)
from several peripherals to the interrupt controller are ORed together to gener-
ate an interrupt request (INTn) to the CPU. This is the core level interrupt re-
quest. There is an interrupt flag bit and an interrupt enable bit located in the
peripheral configuration registers for each event that can cause a PIRQ. There
is also one PIRQ for each event. If an interrupt causing event occurs in a pe-
ripheral and the corresponding interrupt enable bit is set, the interrupt request
from the peripheral to the interrupt controller will be asserted. This interrupt re-
quest simply reflects the status of the peripheral’s interrupt flag, gated with the
interrupt enable bit. When the interrupt flag is cleared, the interrupt request is
cleared.
Some peripherals may have the capability to make either a high-priority or a
low-priority interrupt request. If a peripheral has this capability, the value of its
interrupt priority bit is also transmitted to the interrupt controller. The interrupt
request (PIRQ) continues to be asserted until it is either automatically cleared
by an interrupt acknowledge or cleared by the software.
At the upper level of the hierarchy, the ORed PIRQs generate interrupt (INTn)
requests to the CPU. The request to the ’C240x CPU is a low-going pulse of
two CPU clock cycles. The PIE controller generates an INTn pulse when any
of the PIRQ’s controlling the INTn become active. If any of the PIRQ’s capable
of asserting the CPU interrupt request are still active in the cycle following an
interrupt acknowledge for the INTn, another INTn pulse is generated. An inter-
rupt acknowledge clears the highest priority pending PIRQ. Note that the inter-
rupts are automatically cleared only at the core level and not at the peripheral
level. The interrupt controller (not the peripherals) defines the following:
- Which CPU interrupt request gets asserted by which peripheral
- Relative priority of each peripheral interrupt requests
This is shown in Table 2–2, ’240x Interrupt Source Priority and Vectors , on
page 2-8.