Specifications

Protocol Definitions
C-6
C.2 Protocol Definitions
The transfer of data is done according to a defined protocol for the SPI and
SCI. The protocol for the synchronous transfer over the SPI is discussed in
section C.2.1, and the protocol for the SCI transfer is discussed in sec-
tion C.2.2.
C.2.1 SPI Synchronous Transfer Protocol and Data Formats
The ROM loader expects an 8-bit-wide SPI-compatible EEPROM device to be
present on the SPI pins as indicated in Figure C–1. If the download is to be
performed from a SPI port on another device, then that device must be set up
to operate in the slave mode and mimic a serial EEPROM. Immediately after
entering the SPI loader, the pin functions for the SPI pins are set to primary,
and the SPI is initialized. The initialization is done at the slowest speed pos-
sible. The data transfer is done in “burst” mode for the EEPROM. The transfer
is carried out entirely in byte mode (SPI at 8 bits/character). A step-by-step de-
scription of the sequence follows:
1) The SPI is initialized.
2) The XF pin is now used as a chip-select for the EEPROM.
3) The SPI outputs a read command for the EEPROM (03h).
4) The SPI sends the EEPROM an address 0000h; i.e., the host requires that
the EEPROM must have the downloadable packet beginning at address
0000h in the EEPROM.
5) From this point onward, the next two bytes fetched constitute the destina-
tion address.
The most significant byte of this word is the byte read first, and the
least significant byte is the next byte fetched. This is true of all word
transfers on the SPI.
6) The next word (two bytes) fetched is the length N.
7) The destination is checked to see if it is in the range FE00h to FFFFh. If
necessary, the DARAM block B0 is configured in program memory space.
8) From now on, N words are fetched and stored in program memory at the
address pointed to by destination. The EEPROM is read off in one continu-
ous burst.
9) Finally, once the last word is stored, a simple branch is made into the code
at the destination address; therefore, the entry point for the boot-loaded
code must be at the destination address.