Specifications

Peripheral Interrupt Expansion (PIE)
2-13 System Configuration and Interrupts
Figure 2–5. Peripheral Interrupt Expansion Block Diagram
PIE
CPU
IACK
bus
Addr
bus
Data
PIRQR#
PIACKR#
PIVR#
IRQ GEN
Level 6
IRQ GEN
Level 5
IRQ GEN
Level 4
IRQ GEN
Level 2
IRQ GEN
Level 1
XINT2
XINT1
ADCINT
CANERINT
CANMBINT
TXINT
RXINT
SPIINT
CAP3INT
CAP2INT
CAP1INT
T2OFINT
T2UFINT
T2CINT
T2PINT
T1OFINT
T1UFINT
T1CINT
T1PINT
CMP3INT
CMP2INT
CMP1INT
CANERINT
CANMBINT
TXINT
RXINT
SPIINT
XINT2
XINT1
ADCINT
PDPINTA
IRQ GEN
Level 3
INT1
INT2
INT3
INT4
INT5
INT6
PIRQR0PIRQR1
PDPINTB
T3OFINT
T3UFINT
T3CINT
T3PINT
CMP6INT
CMP5INT
CMP4INT
T4OFINT
T4UFINT
T4CINT
T4PINT
CAP6INT
CAP5INT
CAP4INT