Specifications

Introduction
C-3 TMS320F240x Boot ROM Loader: Protocols and Interfacing
It is suggested that this pin should be driven via a resistor as well,
since if the SPI is used at any time during the operation of the system,
SPISIMO will be an output.
4) Destination check. The incoming destination is now compared to FE00h
to FFFFh. If the destination matches this range, the CNF bit (Bit 12) in the
status register ST1 is set, configuring the DARAM memory block B0 to
Program Memory Space. Any other checks are not preformed and it is en-
tirely up to the host/external boot device to supply a valid combination of
memory destination address and length for the incoming code.This means
that the target code must fit into the internal memory or external memory
must be available.
5) Data transfer. Once the incoming destination and length are fetched (this
protocol is defined in separate sections for the SCI and SPI), the actual
data transfer commences. The fetch is basically destination, length, and
data with no error-checking. On the SCI, the incoming data is echoed
back, allowing the host to implement error-checking, if desired.
6) Execution of incoming code. Once the Boot ROM loader completes
transfer of the packet, a branch is made into the incoming code.
7) Watchdog. The watchdog timer on the device is active during the entire
sequence and is being reset at key points in the code. When a branch is
made into the user code, it is the responsibility of the user code to handle
watchdog overflow as appropriate.
8) Restrictions on the incoming code.
J The combination of the destination address and transfer length must
point to valid locations. There is absolutely no error-handling whatso-
ever.
J The combination also must point to a memory block that is contiguous.
J The address check is performed only on the first location of the incom-
ing destination. It is expected that this allows for enough space for the
rest of the incoming words. This means that if you have external pro-
gram memory at range FDFEh to FDFFh (two words) and you attempt
to load code into the range FDFEh to FEFFh (attempting to use the
internal memory FE00h to FEFFh), this combination is invalid since
the destination check will
not switch B0 into the program space upon
encountering the destination FDFEh. Lastly, the incoming address
and length are expected to be 16 bits, as defined in the SPI and SCI
transfer protocols.