Specifications
Introduction
C-2
C.1 Introduction
The ’240x Digital Signal Processors (DSPs) contain an on-chip read-only
memory (ROM) containing bootloader code. This code loads code from an ex-
ternal serial boot device at reset, and transfers control to the code loaded from
the external device. This chapter describes working with this feature of the
device.
The ’240x device Boot ROM offers the user two options—it can load code
through either asynchronous or synchronous serial transfer.
The synchronous transfer is done through the Serial Peripheral Interface
(SPI), and the asynchronous transfer is done through the Serial Communica-
tions Interface (SCI). The code is loaded to a user-specified location which is
completely flexible—it can be anywhere in program memory where RAM is
available. The serial transfer packet must contain the address as specified in
the applicable Serial Transfer Format, which is described in section C.2.
C.1.1 Boot-Load Sequence
There are a few things that must be set up correctly for the control to transfer
to the Boot ROM and a valid boot load to occur:
1) Micocontroller mode. The ’LF240x device must be placed in microcon-
troller mode, by pulling the MP/MC
pin LOW.
2) Boot ROM loader invocation. The bootloader is invoked by pulling the
BOOT_EN
/XF pin low through a resistor, prior to device reset. This trans-
fers control to the boot-load program located in the on-chip ROM. At reset
time, internal logic takes a “snapshot” of this pin and if this pin is a low level,
then the Boot ROM appears in the memory map as shown in Figure C–2.
Otherwise, the on-chip flash memory is enabled and the program counter
begins execution at 0000h. This pin can be driven high/low from a control
source such as a host processor or through a jumper via a resistor, allow-
ing control of the boot sequence of the DSP. The resistor must be pres-
ent, since the XF pin is an output at all other times.
3) SCI or SPI selection. The bootloader code selects the source of the in-
coming code, depending on the state of the IOPC2 pin on the device. The
code takes a snapshot of this code after being invoked, and determines
which loader (SPI or SCI) to invoke based on the status of this pin.
J If IOPC2 is pulled low, an SCI transfer is commenced
J If IOPC2 is pulled high, an SPI transfer is commenced
J Note that the SPI selection is invalid on devices without the SPI