Specifications

Program Examples
B-37 Program Examples
; 10 – T2 CMP active hi
; 01 – T1 CMP active lo
SPLK #0000000000000000b,T3CNT ; zero timer 3 count
SPLK #0000000000000000b,T4CNT ; zero timer 4 count
SPLK #0001011101000010b,T3CON
; 000 10 Cont, Up
; 111 x/128,
; 0 reserved for T3,Tenable select
; 1 Tenable for Timer 3
; 00 Internal clk
; 00 cntr =0
; 1 enable compare
; 0 use own period register
SPLK #0001011111000011b,T4CON
; TSWT3=1: Use Timer 3 tenable bit
; SELT3PR=1: Use Timer 3 period
; register
SPLK #1111111111111111b,T3PR
SPLK #0011111100000000b,T3CMPR
SPLK #0011111100000000b,T4CMPR
SPLK #0000000000000000b,EVBIMRA
SPLK #0000000000000000b,EVBIMRB
; disable group A,B interrupts
* Load Capture registers
SPLK #0011001001101100b,CAPCONB
; 0 clear capture registers
; 01–enable Capture 4,5 disable QEP
; 1 –enable Capture 6
; 0 –reserved
; 0 –Use GPTimer 4 for CAP6
; 1 –Use GPTimer 3 for CAP4,5
; 0 –No ADC start on CAP6 interrupt
; 01 –CAP4 is rising edge detect
; 10 –CAP5 is falling edge detect
; 11 –CAP6 on both edges
; 00 –reserved
SPLK #0000000000000111b,EVBIMRC
; 0000 0000 0000 0
; 111, enable CAP6,CAP5,CAP4
; interrupts
LDP #6h ; Write the failure code to begin
; with.
SPLK #6101h,61h ; This will be overwritten if the
; test passes
SPLK #6201h,62h
SPLK #6301h,63h
CLRC INTM ; Enable interrupts globally
CALL CAPDLY