Specifications

Peripheral Interrupt Expansion (PIE)
2-12
2.4 Peripheral Interrupt Expansion (PIE)
The ’240x CPU supports one nonmaskable interrupt (NMI) and six maskable
prioritized interrupt requests INT1–INT6 at the core level. The ’240x devices
have many peripherals, and each peripheral is capable of generating one or
more interrupts in response to many events at the peripheral level.
Because the ’C240x CPU does not have sufficient capacity to handle all pe-
ripheral interrupt requests at the core level, a centralized interrupt controller
(PIE) is required to arbitrate the interrupt requests from various sources such
as peripherals and other external pins (see Figure 2–5).