Specifications

Program Examples
B-36
* Load Capture registers
SPLK #0011001001101100b,CAPCONA
; 0 clear capture registers
; 01–enable Capture 1,2 disable QEP
; 1 –enable Capture 3
; 0 –reserved
; 0 –Use GPTimer 2 for CAP3
; 1 –Use GPTimer 1 for CAP1,2
; 0 –No ADC start on CAP3 interrupt
; 01 –CAP1 is rising edge detect
; 10 –CAP2 is falling edge detect
; 11 –CAP3 on both edges
; 00 –reserved
SPLK #0000000000000111b,EVAIMRC
; 0000 0000 0000 0
; 111, enable CAP3,CAP2,CAP1
; interrupts
LDP #6h ; Write the failure code to begin
; with.
SPLK #5101h,51h ; This will be overwritten if the
; test passes
SPLK #5201h,52h
SPLK #5301h,53h
LDP #0
SPLK #0000000000001000b,IMR ; Enable INT4
CLRC INTM ; Enable interrupts globally
CALL CAPDLY
*=====================================================================
* EVB Capture test
* This portion of the code tests the EVB Capture unit. It is assumed
* that the test is failed, unless an interrupt is called (error code 4)
* GISR4 verifies the values in CAPFIFO and reports the results.
* PERIPHERAL CODE : 6, TEST CODE : 1 After successful completion
* of this test case, the value 6100,6200,6300 must be present in 361h,
* 362, 363 (DM) respectively.
*
* Error code: 6101 –– CAP1 value is incorrect
* 6201 –– CAP2 value is incorrect
* 6301 –– CAP3 value is incorrect
*=====================================================================
* Load EVB TIMERS registers
SETC INTM
LDP #GPTCONB >> 7h ; Peripheral page
SPLK #0000000001001001b,GPTCONB
; 0000 0000 0
; 1 – Enable Compare o/ps
; 00 reserved