Specifications

Program Examples
B-18
SPLK #0FFFFh, PBDATDIR ; and forced high
SPLK #0FFFFh, PCDATDIR ;
SPLK #0FFFFh, PEDATDIR ;
SPLK #0FFFFh, PFDATDIR ;
MAIN LDP #0
LAR AR0,#300h ; AR0 points to bit pattern in
; data memory
LAR AR1,#7 ; AR1 is the counter
LOOP MAR *,AR0
LACC *+,AR2 ; Load bit pattern in accumulator
LDP #00E1h
SACL PADATDIR ; Output the same bit pattern
SACL PBDATDIR ; to all the GPIO ports
SACL PCDATDIR
SACL PEDATDIR
SACL PFDATDIR
CALL DELAY ; Delay provided in between
; each pattern
MAR *,AR1 ; Check if all 8 patterns have
BANZ LOOP ; been output. If not, continue.
B MAIN
DELAY LAR AR2,#0FFFFh
D_LOOP RPT #0FFh
NOP
BANZ D_LOOP
RET
PHANTOM KICK_DOG ;Resets WD counter
B PHANTOM