Specifications
Program Examples
B-9
Program Examples
CANMSGID3L .set 7218h ; CAN Message ID for mailbox 3 (lower 16 bits)
CANMSGID3H .set 7219h ; CAN Message ID for mailbox 3 (upper 16 bits)
CANMSGCTRL3 .set 721Ah ; CAN RTR and DLC
CANMBX3A .set 721Ch ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3B .set 721Dh ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3C .set 721Eh ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3D .set 721Fh ; CAN 2 of 8 bytes of Mailbox 3
CANMSGID4L .set 7220h ; CAN Message ID for mailbox 4 (lower 16 bits)
CANMSGID4H .set 7221h ; CAN Message ID for mailbox 4 (upper 16 bits)
CANMSGCTRL4 .set 7222h ; CAN RTR and DLC
CANMBX4A .set 7224h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4B .set 7225h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4C .set 7226h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4D .set 7227h ; CAN 2 of 8 bytes of Mailbox 4
CANMSGID5L .set 7228h ; CAN Message ID for mailbox 5 (lower 16 bits)
CANMSGID5H .set 7229h ; CAN Message ID for mailbox 5 (upper 16 bits)
CANMSGCTRL5 .set 722Ah ; CAN RTR and DLC
CANMBX5A .set 722Ch ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5B .set 722Dh ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5C .set 722Eh ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5D .set 722Fh ; CAN 2 of 8 bytes of Mailbox 5
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; I/O space mapped registers
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WSGR .set 0FFFFh ; Wait–State Generator Control register
FCMR .set 0FF0Fh ; Flash control mode register
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; Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)
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BIT15 .set 0000h ; Bit Code for 15
BIT14 .set 0001h ; Bit Code for 14
BIT13 .set 0002h ; Bit Code for 13
BIT12 .set 0003h ; Bit Code for 12
BIT11 .set 0004h ; Bit Code for 11
BIT10 .set 0005h ; Bit Code for 10
BIT9 .set 0006h ; Bit Code for 9
BIT8 .set 0007h ; Bit Code for 8
BIT7 .set 0008h ; Bit Code for 7
BIT6 .set 0009h ; Bit Code for 6
BIT5 .set 000Ah ; Bit Code for 5
BIT4 .set 000Bh ; Bit Code for 4
BIT3 .set 000Ch ; Bit Code for 3
BIT2 .set 000Dh ; Bit Code for 2
BIT1 .set 000Eh ; Bit Code for 1
BIT0 .set 000Fh ; Bit Code for 0