Specifications

Interrupt Priority and Vectors
2-8
2.3 Interrupt Priority and Vectors
A centralized interrupt expansion scheme is implemented in order to accom-
modate the large number of peripheral interrupts with the six maskable inter-
rupts supported by the CPU. Table 2–2 provides the interrupt source priority
and vectors for the ’240x devices. The details of the ’240x interrupt expansion
scheme are explained in Chapter 2.
Table 2–2. ’240x Interrupt Source Priority and Vectors
Overall
Priority
Interrupt
Name
CPU
Interrupt
Vector
Peripheral
Interrupt
Vector
Maskable?
Source
Peripheral
Description
1 Reset RSN
0000h
N/A N RS Pin,
Watchdog
Reset from pin, watch-
dog time out
2 Reserved –
0026h
N/A N CPU Emulator trap
3 NMI
NMI
0024h
N/A N Nonmaskable
interrupt
Nonmaskable interrupt
(a) INT1 (level 1)
Overall
Priority
Interrupt
Name
CPU
Interrupt
Vector
Peripheral
Interrupt
Vector
Maskable?
Source
Peripheral
Description
4 PDPINTA INT1
0002h
0020h Y EVA Power drive protection
interrupt pin
5 PDPINTB INT1
0002h
0019h Y EVB Power drive protection
interrupt pin
6 ADCINT INT1
0002h
0004h Y ADC ADC interrupt in high-
priority mode
7 XINT1 INT1
0002h
0001h Y External
interrupt logic
External interrupt pin in
high-priority mode
8 XINT2 INT1
0002h
0011h Y External
interrupt logic
External interrupt pin in
high-priority mode
9 SPIINT INT1
0002h
0005h Y SPI SPI interrupt in high-
priority mode
10 RXINT INT1
0002h
0006h Y SCI SCI receiver interrupt
in high-priority mode
11 TXINT INT1
0002h
0007h Y SCI SCI transmitter inter-
rupt in high-priority
mode
12 CANMBINT INT1
0002h
0040h Y CAN CAN mailbox interrupt
(high-priority mode)
13
CANERINT INT1
0002h
0041h Y CAN CAN error interrupt
(high-priority mode)