Specifications

Digital I/O (GPIO Pins)
13-22
Table 13–10. ’LF2407 Shared Pin Configuration (Continued)
Shared Pin Functions
IOP
Direction
Bit #
IOP Data
Bit #
IOP Data
and
Direction
Register
MCRx.n
Value at
Reset
Mux
Control
Bit #
Mux
Control
Register
Primary
Function (1)
IOP
Direction
Bit #
IOP Data
Bit #
IOP Data
and
Direction
Register
MCRx.n
Value at
Reset
Mux
Control
Bit #
Mux
Control
Register
I/O (0)
XINT2/ADCSOC IOPD0 MCRB 8 0 PDDATDIR 0 8
EMU0 IOPD1 Reserved 9 1 PDDATDIR – –
EMU1 IOPD2 Reserved 10 1 PDDATDIR – –
TCK IOPD3 Reserved 11 1 PDDATDIR – –
TDI IOPD4 Reserved 12 1 PDDATDIR – –
TDO IOPD5 Reserved 13 1 PDDATDIR – –
TMS IOPD6 Reserved 14 1 PDDATDIR – –
TMS2 IOPD7 Reserved 15 1 PDDATDIR – –
CLKOUT
IOPE0 MCRC 0 1 PEDATDIR 0 8
PWM7 IOPE1 MCRC 1 0 PEDATDIR 1 9
PWM8 IOPE2 MCRC 2 0 PEDATDIR 2 10
PWM9 IOPE3 MCRC 3 0 PEDATDIR 3 11
PWM10 IOPE4 MCRC 4 0 PEDATDIR 4 12
PWM11 IOPE5 MCRC 5 0 PEDATDIR 5 13
PWM12 IOPE6 MCRC 6 0 PEDATDIR 6 14
CAP4/QEP3 IOPE7 MCRC 7 0 PEDATDIR 7 15
CAP5/QEP4 IOPF0 MCRC 8 0 PFDATDIR 0 8
CAP6 IOPF1 MCRC 9 0 PFDATDIR 1 9
T3PWM/CMP IOPF2 MCRC 10 0 PFDATDIR 2 10
T4PWM/CMP IOPF3 MCRC 11 0 PFDATDIR 3 11
TDIRB IOPF4 MCRC 12 0 PFDATDIR 4 12
TCLKINB IOPF5 MCRC 13 0 PFDATDIR 5 13
IOPF6
IOPF6 X X X PFDATDIR 6 14