Specifications

Digital I/O (GPIO Pins)
13-21 ’24x–’240x Family Compatibility
Table 13–10. ’LF2407 Shared Pin Configuration
Shared Pin Functions
Mux Mux MCRx.n
IOP Data
and
IOP Data
IOP
Primary
Function (1)
I/O (0)
M
u
x
Control
Register
M
u
x
Control
Bit #
MCRx
.
n
Value at
Reset
and
Direction
Register
IOP Data
Bit #
IOP
Direction
Bit #
SCITXD
IOPA0 MCRA 0 0 PADATDIR 0 8
SCIRXD IOPA1 MCRA 1 0 PADATDIR 1 9
XINT1 IOPA2 MCRA 2 0 PADATDIR 2 10
CAP1/QEP1 IOPA3 MCRA 3 0 PADATDIR 3 11
CAP2/QEP2 IOPA4 MCRA 4 0 PADATDIR 4 12
CAP3 IOPA5 MCRA 5 0 PADATDIR 5 13
PWM1 IOPA6 MCRA 6 0 PADATDIR 6 14
PWM2 IOPA7 MCRA 7 0 PADATDIR 7 15
PWM3 IOPB0 MCRA 8 0 PBDATDIR 0 8
PWM4 IOPB1 MCRA 9 0 PBDATDIR 1 9
PWM5 IOPB2 MCRA 10 0 PBDATDIR 2 10
PWM6 IOPB3 MCRA 11 0 PBDATDIR 3 11
T1PWM/CMP IOPB4 MCRA 12 0 PBDATDIR 4 12
T2PWM/CMP IOPB5 MCRA 13 0 PBDATDIR 5 13
TDIRA IOPB6 MCRA 14 0 PBDATDIR 6 14
TCLKINA IOPB7 MCRA 15 0 PBDATDIR 7 15
W/R
IOPC0 MCRB 0 1 PCDATDIR 0 8
BIO IOPC1 MCRB 1 1 PCDATDIR 1 9
SPISIMO IOPC2 MCRB 2 0 PCDATDIR 2 10
SPISOMI IOPC3 MCRB 3 0 PCDATDIR 3 11
SPICLK IOPC4 MCRB 4 0 PCDATDIR 4 12
SPISTE IOPC5 MCRB 5 0 PCDATDIR 5 13
CANTX IOPC6 MCRB 6 0 PCDATDIR 6 14
CANRX
IOPC7 MCRB 7 0 PCDATDIR 7 15