Specifications

Digital I/O (GPIO Pins)
13-20
13.6 Digital I/O (GPIO Pins)
Some members of the ’240x family have more GPIO pins than the ’24x de-
vices. This necessitates additional registers. The bit definitions for some multi-
plexed pins such as XF, CLKOUT, etc. are different from those of the ’24x. See
Chapter 5 for more details.
Note that when multiplexed I/O pins are in input mode, the pin is connected
to both the I/O data register and the shared peripheral. The I/O Mux control
register (MCRx) in ’240x devices is synonymous to the OCRx in ’24x devices.
Both MCRx and OCRx have the same function in ’240x and ’24x devices,
respectively.
13.6.1 Digital I/O and Shared Pin Functions for the ’240x
’LF2407 device has a total of 41 pins shared between Primary functions and
I/Os.
Table 13–10 lists all the pins that are shared between the Primary functions
and the dedicated I/O Ports A, B, C, D, E, F.