Specifications

System Features
13-19 ’24x–’240x Family Compatibility
13.5.3.2 Fast RD Strobe Operation
’LF2407 is the only device that supports external memory interface (XMIF) to
expand the internal memory space with the addition of external memory de-
vices. The interface offers decode signals for Program, Data, and I/O space.
’LF2407 external memory interface signals have critical timings while interfac-
ing zero-wait-state memory at higher CPU clock speeds. CPU memory reads
are single-cycle and read-enable (RD
) timing is critical to meet the output-
enable timing for memories that can be interfaced to this device. To alleviate
the memory read interface timing, an additional signal W/R
is provided to be
used as output-enable signal instead of RD. W/R is essentially an inverted
R/W signal from the core. The W/R signal will remain all the time from reset
and will go high during external write cycles. Refer to the memory interface tim-
ings in the TMS320LF2407, TMS320LF2406, TMS320LF2402,
TMS320LC2406, TMS320LC2404, TMS320LC2402 DSP Controllers Data
Sheet (literature number SPRS094) for additional timing details.
Figure 13–9. Functional Block Diagram of XMIF Signals on ’LF2407
’C2xx
CPU
core
XMIF
module
Address bus
Data bus
Control bus
RD
R/W
’LF2407 DSP
External pins
A0–A15
D0–D15
PS
, DS, IS,
STRB
, R/W,
WR
RD
W/R/IOPC0