Specifications

System Features
13-18
13.5.3 System Control Registers
’240x devices have two system control and status registers: SCSR1 and
SCSR2 (see section 2.2.1 on page 2-3). These registers have control and sta-
tus bits for several on-chip modules. These register bits should be initialized
after reset to enable/disable on-chip functionality for the selected application.
’24x has only one SCSR register and all its on-chip peripherals are powered
up after reset. The SCSR2 register is unique to ’240x and its peripherals are
disabled after reset.
13.5.3.1 Boot_EN/XF Pin Operation
During the Reset phase (i.e., RS low), this pin functions as a Boot_EN input
pin, and its logic level is latched into bit 3 of the SCSR2 register. If the bit is set
to 1, Boot ROM is active.
At the completion of the Reset phase (rising edge of RS), this pin will be XF
output (“external flag”) function, and the Boot_EN function is no longer avail-
able through this pin. However, the Boot_EN
bit in SCSR2 can be used to con-
trol the visibility of the Boot ROM or the Flash array.
Figure 13–8. Functional Block Diagram for Boot_EN/XF Feature
SCSR2 Boot En
Boot_EN
Boot_EN/XF
pin
RS
XF (from core)
Operating Mode
Program Memory
Active for the CPU
Boot_EN Pin /
SCSR2 Bit 3
Comment
Functional Boot ROM: 0x0000–0x00FF 0
Can be changed later by
software bit in SCSR2
Functional Flash Array: 0x0000–0x7FFF 1
Can be changed later by
software bit in SCSR2