Specifications

System Features
13-17 ’24x–’240x Family Compatibility
13.5.2 Watchdog Clock
Watchdog clock generation logic is different in ’240x devices with respect to
’24x devices. Unlike the fixed PLL (x4) in ’24x, the ’240x devices have a vari-
able clock from the PLL. This changes the input clock options for the watch-
dogmodule. The clock flow diagram below explains the watchdog clock gener-
ation logic.
’240x devices have a watchdog override bit in the SCSR2 register, which is
similar to the WDDIS pin available on the ’24x devices. Refer to the description
of SCSR2 register bit 5 (section 2.2.1 on page 2-3) for details on this bit
function.
Figure 13–7. ’240x Watchdog Clock Generation Logic
Oscillator clock/
External clock
3-bit ratio selector
PLL
/512
Watchdog module
WDCLK
CLKOUT
13.5.2.1 Other Low-Power Management Features
All ’240x devices have a clock-enable bit in the SCSR1 register to save power
and selectively enable peripheral functions. At reset, these peripheral clock-
enable bits are disabled, and the applications software should enable the re-
quired modules. The peripheral clocks of the following peripherals can be in-
dependently enabled/disabled. See section 2.2.1 on page 2-3 for bit descrip-
tions of the SCSR1 register.
Table 13–9. Peripheral Clock Enable Bits
Peripheral SCSR1 Bits Description
EVA SCSR1.2 Event Manager A
EVB SCSR1.3 Event Manager B
CAN SCSR1.4 Controller Area Network
SPI SCSR1.5 Serial Peripheral Interface
SCI SCSR1.6 Serial Communications Interface
ADC
SCSR1.7 Analog-to-Digital Converter