Specifications

System Features
13-16
13.5 System Features
This section presents some the system features that are new to the ’240x de-
vices. Understanding these key features may help system initialization and
’24x-to-’240x migration.
13.5.1 Oscillator and PLL
Unlike the ’24x device, the ’240x devices have a 5-pin PLL with a 3-bit ratio
control to provide eight different CPU clock options. Table 13–7 describes the
pins that are used for the PLL/Oscillator module and Table 13–8 lists the oscil-
lator/PLL frequency input specification. PLL is preceded by an on-chip oscilla-
tor, which can accept a resonator or a crystal. The PLL accepts the on-chip
oscillator or external clock as its input clock. Refer to the TMS320LF2407,
TMS320LF2406, TMS320LF2402, TMS320LC2406, TMS320LC2404,
TMS320LC2402 DSP Controllers Data Sheet (literature number SPRS094)
for clock circuits and recommended values for the external filter components.
Table 13–7. ’240x PLL Pin Names
Pin Names Description
XTAL1/CLKIN
Oscillator input, crystal and ceramic resonator input, or
external clock input
XTAL2 Used only by crystal or ceramic resonators as an output
PLLF PLL loop filter terminal 1
PLLV
CCA
PLL supply (3.3 V), to be connected to digital supply
PLLF2
PLL loop filter termianl 2
Table 13–8. Oscillator/PLL Frequency Input Specification
Value
Input crystal frequency range 4–20 MHz
Input ceramic resonator frequency range 4–13 MHz
Input oscillator/CLOCKIN frequency range
4–20 MHz