Specifications

Flash Program Memory
13-14
Bits 15–3 Reserved
Bit 2 TCR Enable. Test Control Register Enable
This bit enables the Test Control Register (TCR) to the specific core corre-
sponding to this ENAB register. This controls the TEZ input to the Flash core.
This bit is only accessible if the TEST input is high.
Bit 1 Standby. Standby mode Enable
This bit, when active high, puts the Flash core into standby mode. In this mode,
the Flash core goes into a very low current consumption mode, and the Flash
core cannot be read. To read the Flash core again, this bit must be cleared first.
This controls the SENSE input to the Flash core, which controls whether the
sense amp is on or off.
Bit 0 CNTL Enable. Control Register Enable
This bit gates the Flash Control Register (CTRL) to the specific core corre-
sponding to this ENAB register. It enables the following Flash operations to the
Flash core: PROG, PROGVER, ERASE, ERASEVER, CMPCT, CMPCTVER,
RDMRGN0, RDMRGN1, REDU, ENGR0, ENGR1, ENGR2, NOROWRED,
and PRECOND. This controls the CTRLENZ input to the Flash core.
13.4.2.4 Sector Enable Register
Figure 13–6. Sector Enable Register
15–8
Reserved
R-x
7–4 3210
Reserved
Sect 4
Enable
Sect 3
Enable
Sect 2
Enable
Sect 1
Enable
R-x RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset, x = undefined