Specifications

Flash Program Memory
13-11 ’24x–’240x Family Compatibility
Bits 15–4 Reserved
Bit 3 PWR DWN. Power down bit
Writing a 1 to this bit puts the Flash pumps into a very low current consumption
mode. This register bit is mostly intended for test purposes; however, this bit
can be used in normal operating mode also, if needed. Powerdown mode is
entered if the PWRD bit is set high.
Bit 2 KEY1. Execute key bit 1
This bit must be written as a 1 in the same access as the EXEC bit is set for
the EXECUTE operation to start. This bit is used as additional protection
against inadvertent programming or erasing of the Flash.
Bit 1 KEY0. Execute key bit 0
This bit must be written as a 0 in the same access as the EXEC bit is set for
the EXECUTE operation to start. This bit is used as additional protection
against inadvertent programming or erasing of the Flash.
Bit 0 EXEC. Execute
This bit initiates and ends programming, erasing, and compaction to the Flash
array. The EXEC bit and the KEY0/1 bits must be written in the same write ac-
cess. When the operation time has expired, the EXEC bit should be cleared
in the same write as the KEY0/1 bits. The data and address latches are locked
whenever the EXEC bit is set and all attempts to read from or write to the array
will be ignored (read data will be indeterminate). This bit controls the EXECU-
TEZ signal on the Charge Pump module.
13.4.2.2 Flash Control Register
Figure 13–4. Flash Control Register
15–10 9 8
Reserved WSVER En
PRECND
Mode1
R-x R-x R-x
76543210
PRECND
Mode0
ENG/R
Mode2
ENG/R
Mode1
ENG/R
Mode0
FCM3 FCM2 FCM1 FCM0
R-x R-x R-x R-x R-x R-x R-x R-x
Note: R = Read access, x = undefined