Specifications

Flash Program Memory
13-10
Table 13–6. Flash Control Registers in Flash Control Mode
Name Program Address Description
PMPC XXX0h
Pump Control Register.
This register controls the charge pump. It contains the EXECUTE
bit, two KEY bits that offer protection against inadvertent program-
ming or erasing, and the PWRD bit that is used as an alternative to
the POWERDOWN input signal.
CTRL XXX1h
Flash Control Register.
This register controls all modes of operation on the Flash array,
such as programming, erasing, and compaction.
WADDR XXX2h
Write Address Register.
This register holds the address for a write operation. It is also used
during an erase operation to define which sector of Flash is to be
erased.
WDATA XXX3h
Write Data Register.
This register holds the data for a write operation. It is also used
during an erase operation as a key to prevent inadvertent erases.
TCR XXX4h
Test Control Register.
This register is used for test operations. It is not accessible in nor-
mal operation.
ENAB XXX5h Flash Core Enable Register – Reserved
SECT
XXX6h
Sector Enable Register.
This register has four bits to enable the four sectors of the array for
programming and erasing operations.
13.4.2.1 Pump Control Register
Figure 13–3. Pump Control Register
15–8
Reserved
R-x
7–4 3210
Reserved PWR DWN KEY1 KEY0 EXEC
R-x RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset, x = undefined