Specifications

General
12-2
12.1 General
Low-power mode 2 (HALT) is the lowest power mode on the ’240x. It is similar
to the LPM3 (oscillator power down) on the ’240. There is no equivalent to
LPM2 (PLL power down) on the ’240. The low-power-mode bits are in a differ-
ent register (SCSR1) and in different bit positions on the ’240x.
Software reset is not available. However a software reset can be achieved by
writing an incorrect key to the watchdog timer after setting a flag in memory
to indicate that this was a software reset, and not a true watchdog time-out.
Illegal address detect does not have 100% coverage on the ’240; however, it
does on ’240x devices. Furthermore, an illegal address generates a reset on
the ’240, and an NMI on the ’240x. The NMI service routine must poll the IL-
LADDR bit in SCSR1 to determine whether the NMI was caused by an illegal
address or the NMI pin.
External interrupts XINT2 and XINT3 on the ’240 are similar to external inter-
rupts XINT1 and XINT2 on the ’240x. The addresses of the registers are differ-
ent, however, and the general-purpose I/O multiplexing control bits are located
in the digital I/O registers, not in the external interrupt control registers. The
external interrupt flags are cleared by writing a 1 to the flag bit. This is in order
to be consistent with the other peripherals.
The CLOCKOUT control bits are in a different register (SCSR1) and bit
position.