Specifications

Configuration Registers

2-5

System Configuration and Interrupts

Bit 1 Reserved

Bit 0 ILLADR. Illegal Address detect bit

If an illegal address has occurred this bit will be set. It is up to software to clear

this bit following an illegal address detect. Note: An illegal address will cause

an NMI.

Figure 2–3. System Control and Status Register 2 (SCSR2) — Address 07019h

15–8

Reserved

RW-0

7–6 543210

Reserved

OVERRIDE

XMIF_HI-Z BOOT_EN MP/MC DON PON

RW-0 RW-1 RW-0 RW-

BOOT_EN

RW-

MP/MC

RW-1 RW-1

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15–6 Reserved. Writes have no effect, read are undefined

Bit 5 Watchdog Override. (WD protect bit)

After RESET, this bit gives the user the ability to disable the WD function

through software (by setting the WDDIS bit = 1 in the WDCR). This bit is a clear

only bit and defaults to a 1 after reset,

Note: this bit is cleared by writing a 1

to it.

0 Protects the WD from being disabled by software. This bit cannot

be set to 1 by software. It is a clear-only bit, cleared by writing a 1.

1 This is the default reset value and allows the user to disable the

WD through the WDDIS bit in the WDCR.

Once cleared however, this bit can no longer be set to 1 by soft-

ware, thereby protecting the integrity of the WD timer.

Bit 4 XMIF_Hi-Z Control

This bit controls the state of the external memory interface (XMIF) signals.

0 XMIF signals in normal driven mode, i.e., not Hi-Z (high impedance)

1 All XMIF signal are forced to Hi-Z state