Specifications

Watchdog Control Registers
11-10
Bit 4 WDCHK1. Watchdog Check Bit 1. This bit must be written as a 0 when you
write to the WDCR register, or else a system reset is asserted. This bit is al-
ways read as 0.
0 Normal operation continues if all check bits are written correctly.
1 System reset is asserted.
Bit 3 WDCHK0. Watchdog Check Bit 0. This bit must be written as a 1 when you
write to the WDCR register, or else a system reset is asserted. This bit is al-
ways read as 0.
0 System reset is asserted.
1 Normal operation continues if all check bits are written correctly.
Bits 2–0 WDPS2–WDPS0. Watchdog Prescale Select Bits. These bits select the
counter overflow tap that is used to clock the WD counter. Each selection sets
up the maximum time that can elapse before the WD key logic is serviced.
Table 11–3 show the overflow times for each prescaler setting when the
WDCLK is running at 58593.8 Hz. Because the WD timer counts 257 clocks
before overflowing, the times given are the minimum for overflow (reset). The
maximum timeout can be up to 1/256 longer than the times listed in Table 11–3
because of the added uncertainty resulting from not clearing the prescaler.
Table 11–3. WD Overflow (Timeout) Selections
WD Prescale Select Bits 58593.8 kHz WDCLK
†
WDPS2 WDPS1 WDPS0
WDCLK
Divider
Overflow
Frequency
(Hz)
Minimum
Overflow
(ms)
0 0 X 1 228.9 4.36
0 1 0 2 114.4 8.7
0 1 1 4 57.2 17.5
1 0 0 8 28.6 35
1 0 1 16 14.3 69.9
1 1 0 32 7.15 139.8
1
1 1 64 3.6 279.6
X = Don’t care
†
Generated by a 30-MHz clock