Specifications

Watchdog Control Registers
11-9 Watchdog (WD) Timer
11.3.2 WD Reset Key Register
The WD reset key register clears the WDCNTR register when a 55h followed
by an AAh is written to WDKEY. Any combination of AAh and 55h is allowed,
but only a 55h followed by an AAh resets the counter. Any other value causes
a system reset.
Figure 11–3.WD Reset Key Register (WDKEY) — Address 7025h
76543210
D7
D6 D5 D4 D3 D2 D1 D0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 7–0 D7–D0. Data Values. These write-only data bits contain the 8-bit WD reset key
value. When read, the WDKEY register does not return the last key value but
rather returns the contents of the WDCR register.
11.3.3 WD Timer Control Register
WDCR contains control bits used for watchdog configuration. These include
flag bits that indicate if the WD timer initiated a system reset; check bits that
assert a system reset if an incorrect value is written to the WDCR register; and
watchdog prescale select bits that select the counter overflow tap which is
used to clock the WD counter.
Figure 11–4.WD Timer Control Register (WDCR) — Address 7029h
76543210
Reserved WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0
RC-x RWc-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, C = Clear by writing 1, W = Write access, Wc = Write access conditional on VCCP or WDDIS pins high,
-0 = value after reset, -x = value after reset determined by action/inaction of WD timer
Bit 7 Reserved
Bit 6 WDDIS. Watchdog Disable. This bit can be written only when the VCCP (on
Flash devices) or the WDDIS pin (on ROM devices) is high.
0 Watchdog is enabled.
1 Watchdog is disabled.
Bit 5 WDCHK2. Watchdog Check Bit 2. This bit must be written as a 1 when you
write to the WDCR register, or else a system reset is asserted. This bit is al-
ways read as 0.
0 System reset is asserted.
1 Normal operation continues if all check bits are written correctly.