Specifications

Watchdog Control Registers
11-8
11.3 Watchdog Control Registers
The WD module control registers are shown in Table 11–2 and discussed in
detail in the following subsections.
Table 11–2. WD Module Control Registers
Bit Number
Address
Register
mnemonic
7 6 5 4 3 2 1 0
7020h — Reserved
7021h — Reserved
7022h — Reserved
7023h WDCNTR D7 D6 D5 D4 D3 D2 D1 D0
7024h — Reserved
7025h WDKEY D7 D6 D5 D4 S3 S2 D1 D0
7026h — Reserved
7027h — Reserved
7028h — Reserved
7029h WDCR Reserved WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0
11.3.1 WD Counter Register
The 8-bit WD counter register (WDCNTR) contains the current value of the WD
counter. This register continuously increments at a rate selected through the
WD control register. When WDCNTR overflows, an additional single-cycle
delay (either WDCLK or WDCLK divided by a prescale value) is incurred be-
fore system reset is asserted. Writing the proper sequence to the WD reset key
register clears WDCNTR and prevents a system reset. However, it does not
clear the free-running counter.
Figure 11–2.WD Counter Register (WDCNTR) — Address 7023h
76543210
D7
D6 D5 D4 D3 D2 D1 D0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Note: R = Read access, -0 = value after reset
Bits 7–0 D7–D0. Data Values. These read-only data bits contain the 8-bit WD counter
value. Writing to this register has no effect.