Specifications

Control Registers
11-7 Watchdog (WD) Timer
11.2.4.2 WD Check Bit Logic
The WD check bits (WDCR.5–3, described in detail in section 11.3.3 on
page 11-9) are continuously compared to a constant value (101
2
). If writes
to the WD check bits do not match this value, a system reset is generated. This
functions as a logic check, in case the software improperly writes to the
WDCR, or if an external stimulus (such as voltage spikes, EMI, or other disrup-
tive sources) corrupt the contents of the WDCR. Writing to bits WDCR.5-3 with
anything but the correct pattern (101
2
) generates a system reset.
The check bits are always read as zeros (000
2
), regardless of what value has
been written to them.
11.2.4.3 WD Setup
The WD timer operates independently of the CPU and is always enabled. It
does not need any CPU initialization to function. When a system reset occurs,
the WD timer defaults to the fastest WD timer rate available (4.36 ms for a
58593.8-Hz WDCLK signal). As soon as reset is released internally, the CPU
starts executing code, and the WD timer begins incrementing. This means
that, to avoid a premature reset, WD setup should occur early in the power-up
sequence.