Specifications

Control Registers
11-6
Table 11–1 shows a typical sequence written to WDKEY after power-up.
Table 11–1. Typical WDKEY Register Power-Up Sequence
Sequential
Step
Value Written
to WDKEY
Result
1 AAh No action.
2 AAh No action.
3 55h WDCNTR is enabled to be reset by the next AAh.
4 55h WDCNTR is enabled to be reset by the next AAh.
5 55h WDCNTR is enabled to be reset by the next AAh.
6 AAh WDCNTR is reset.
7 AAh No action.
8 55h WDCNTR is enabled to be reset by the next AAh.
9 AAh WDCNTR is reset.
10 55h WDCNTR is enabled to be reset by the next AAh.
11
23h System reset due to an improper key value writ-
ten to WDKEY.
Step 3 above is the first action that enables the WDCNTR to be reset. The
WDCNTR is not actually reset until step 6. Step eight re-enables the WDCNTR
to be reset, and step 9 resets the WDCNTR. Step 10 again reenables the
WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11
causes a system reset.
A WDCNTR overflow or an incorrect key value written to the WDKEY also sets
the WD flag (WDFLAG). After a reset, the program reads this flag to determine
the source of the reset. After reset, WDFLAG should be cleared by the soft-
ware to allow the source of subsequent resets to be determined. WD resets
are not prevented when the flag is set.
11.2.4.1 WD Reset
When the WDCNTR overflows, the WD timer asserts a system reset. Reset
occurs one WDCNTR clock cycle (either WDCLK or WDCLK divided by a pres-
cale value) later. The reset cannot be disabled in normal operation as long as
WDCLK is present. The WD timer is, however, disabled in the oscillator power-
down mode when WDCLK is not active. For software development or flash
programming purposes, the WD timer can be disabled by setting the WDDIS
bit in the WD control register (WDCR.6). Note that there is no WDDIS pin in
the ’240x devices.