Specifications

Control Registers
11-4
11.2 Control Registers
Three registers control the WD operations:
- WD Counter Register (WDCNTR) — This register contains the value of
the WD counter.
- WD Key Register (WDKEY) — This register clears the WDCNTR when a
55h value followed by an AAh value is written to WDKEY.
- WD Control Register (WDCR) — This register contains the following con-
trol bits used for watchdog configuration
J WD disable bit
J WD flag bit
J WD check bits (three)
J WD prescale select bits (three)
The Watchdog Timer Clock is a low-frequency clock (WDCLK) is used to clock
the Watchdog Timer. WDCLK has a nominal frequency of 58593.8 Hz when
CPUCLK = 30 MHz. WDCLK is derived from the CLKOUT of the CPU. This
ensures that the Watchdog continues to count when the CPU is in IDLE1 or
IDLE 2 mode (see the section on Low-Power Modes). WDCLK is generated
in the Watchdog peripheral. The frequency of WDCLK can be calculated from:
WDCLK = (CLKOUT)/512
WDCLK is seen at the CLKOUT pin only when the Watchdog is enabled. If the
watchdog is enabled, the watchdog counter should be reset before it over-
flows; otherwise, the DSP will be reset.
11.2.1 Watchdog Suspend
WDCLK is stopped when the CPU’s suspend signal goes active. This is
achieved by stopping the clock input to the clock divider which generates
WDCLK from CLKOUT.
Note that the watchdog timer clock does not run when the real-time monitor
is running. This is different from the ’F/C240.