Specifications

Watchdog Timer Features
11-3 Watchdog (WD) Timer
Figure 11–1.Block Diagram of the WD Module
6-bit free-
running
counter
CLR
WDCLK
System reset
WD prescale
select bits
WDCR.2–0
WDPS2–0
WDCR.6
WDDIS
WDKEY.7–0
Watchdog
reset key
register
55+AA
detector
Bad key
Good
key
8-bit watchdog
counter
CLR
WDCHK2–0
WDCR.5–3{
011
WDCNTR.7–0
1-cycle
delay
WD FLAG
WDCR.7
System
reset
request
Bad WDCR key
3
3
PS/257
(Constant value)
Prescale
selection
111
110
101
100
011
001
010
000
/2}
/4}
/8}
/16}
/32}
/64}
Register
Name
WDCNTR Watchdog Counter Register
WDKEY Watchdog Reset Key Register
WDCR Watchdog Control Register
{ Writing to bits WDCR.5–3 with anything but the correct pattern (101) generates a system reset.
} These prescale values are with respect to the WDCLK signal.