Specifications

Configuration Registers
2-4
Bits 11–9 PLL Clock prescale select. These bits select the PLL multiplication factor for
the input clock.
CLK
PS2
CLK
PS1
CLK
PS0
System Clock Frequency
0 0 0 4 x F
in
0 0 1 2 x F
in
0 1 0 1.33 x F
in
0 1 1 1 x F
in
1 0 0 0.8 x F
in
1 0 1 0.66 x F
in
1 1 0 0.57 x F
in
1 1 1 0.5 x F
in
Note: F
in
is the input clock frequency.
Bit 8 Reset OSC Fail. Reset if Oscillator fails
0 System reset is NOT initiated if the clock monitor detects a bad
oscillator input.
1 System reset is initiated if the clock monitor detects a bad oscillator
input.
Bit 7 ADC CLKEN. ADC module clock enable control bit
0 Clock to module is disabled (i.e. shut down to conserve power)
1 Clock to module is enabled and running normally
Bit 6 SCI CLKEN. SCI module clock enable control bit
0 Clock to module is disabled (i.e. shut down to conserve power)
1 Clock to module is enabled and running normally
Bit 5 SPI CLKEN. SPI module clock enable control bit
0 Clock to module is disabled (i.e. shut down to conserve power)
1 Clock to module is enabled and running normally
Bit 4 CAN CLKEN. CAN module clock enable control bit
0 Clock to module is disabled (i.e. shut down to conserve power)
1 Clock to module is enabled and running normally
Bit 3 EVB CLKEN. EVB module clock enable control bit
0 Clock to module is disabled (i.e. shut down to conserve power)
1 Clock to module is enabled and running normally
Bit 2 EVA CLKEN. EVA module clock enable control bit
0 Clock to module is disabled (i.e. shut down to conserve power)
1 Clock to module is enabled and running normally