Specifications

Suspend Mode
10-38
10.9 Suspend Mode
The suspend mode can operate in either Free mode , where the CAN peripher-
al continues to operate regardless of the suspend signal being active, or Soft
mode , where the CAN peripheral stops operation at the end of the current
transmission. Suspend mode is entered when the CPU activates the SUS-
PEND signal. The SUSP bit in MCR determines which of the two suspend
modes (
Free or Soft ) is entered.
When the module enters the Soft suspend mode, the status bit SMA is set. If
the module is actually transmitting a message when the SUSPEND signal is
activated, the transmission is continued until a successful transmission, a lost
arbitration, or an error condition on the CAN bus line occurs. Otherwise, it en-
ters suspend mode immediately and sets the SMA bit.
In Free mode, the peripheral ignores the suspend signal and continues to op-
erate, receiving and transmitting messages.
Either way, the module causes no error condition on the CAN bus line.
When suspended (in Soft mode), the module does not send or receive any
messages. The module is not active on the CAN bus line. Acknowledge flags
and error flags are not sent. The error counters and all other internal registers
are frozen. Suspend is only asserted when a system is being debugged with
an in-circuit emulator.
In case the module is in bus-off mode when suspend mode is requested, it en-
ters suspend mode immediately. It does, however, still count the 128 × 11 re-
cessive bits needed to return to the bus-on mode. All error counters are unde-
fined in that state. The bus-off flag and the error-passive flag are set.
The module leaves the suspend mode when the SUSPEND signal is deacti-
vated. It waits for the next 11 recessive bits on the bus and goes back to normal
operation. This is called the idle mode (different from the CPU’s IDLE mode).
The module waits for the next message or tries to send one itself. When the
module is in bus-off mode, it continues to wait for the bus-on condition. This
occurs when 128 × 11 recessive bits are received. It also counts those that oc-
curred during the suspend mode.
Note: The clock is not switched off internally for suspend or low-power mode.
For easy reference, Table 10–5 provides a listing of the notation, definition,
and register and bit number.