Specifications

Interrupt Logic
10-35 CAN Controller Module
10.6.2 CAN Interrupt Mask Register (CAN_IMR)
The setup for the interrupt mask register (see Figure 10–22) is the same as
for the interrupt flag register (CAN_IFR) with the addition of the interrupt prior-
ity selection bits MIL and EIL. If a mask bit is set, the corresponding interrupt
request to the PIE controller is enabled.
Figure 10–22. CAN Interrupt Mask Register (CAN_IMR) — Address 710Ah
15 14 13 12 11 10 9 8
MIL
Reserved MIM5 MIM4 MIM3 MIM2 MIM1 MIM0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
EIL
RMLIM AAIM WDIM WUIM BOIM EPIM WLIM
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access; W = Write access; value following dash (–) = value after reset
Two additional control bits are included in this register:
Bit 15 MIL. Mailbox Interrupt Priority Level
For the mailbox interrupts MIF5 – MIF0.
0 The mailbox interrupts generate high-priority requests; that is, on line
CAMBOXIRQn with CAMBOXPRI set to 1.
1 The mailbox interrupts generate low-priority requests; that is, on line
CAMBOXIRQn with CAMBOXPRI set to 0.
Bit 14 Reserved
Bit 7 EIL. Error Interrupt Priority Level
For the error interrupts RMLIF, AAIF, WDIF, WUIF, BOIF, EPIF, and WLIF.
0 The named interrupts generate high-priority requests; that is, on line
CAERRIRQn with CAERRPRI set to 1.
1 The named interrupts generate low-priority requests; that is, on line
CAERRIRQn with CAERRPRI set to 0.
NOTE: For description of bits 13–8 and bits 6–0, refer to section 10.6.1.