Specifications

Interrupt Logic
10-34
There is one interrupt mask bit for each mailbox. If a message is received, the
corresponding bit RMPn in the RCR is set. If a message is sent, the corre-
sponding bit TA in the TCR register is set. The setting of the RMPn bit or the
TAn bit also sets the appropriate MIFx flag in the IF register if the correspond-
ing interrupt mask bit is set. The MIFx flag generates an interrupt. The MIMx
mask bits determine if an interrupt can be generated by a mailbox.
Bit 7 Reserved.
Bit 6 RMLIF. Receive Message Lost Interrupt Flag
0 No message was lost.
1 An overflow condition has occurred in at least one of the receive
mailboxes.
Bit 5 AAIF. Abort Acknowledge Interrupt Flag
0 No transmission was aborted.
1 A send transmission was aborted.
Bit 4 WDIF. Write Denied Interrupt Flag
0 The write access to the mailbox was successful.
1 The CPU tried to write to a mailbox but was not allowed to.
Bit 3 WUIF. Wake-Up Interrupt Flag
0 The module is still in the sleep mode or in normal operation.
1 The module has left the sleep mode.
Bit 2 BOIF. Bus Off Interrupt Flag
0 The CAN module is still in the bus-on mode.
1 The CAN has entered the bus-off mode.
Bit 1 EPIF. Error Passive Interrupt Flag
0 The CAN module is not in the error-passive mode.
1 The CAN module has entered the error-passive mode.
Bit 0 WLIF. Warning Level Interrupt Flag
0 None of the error counters has reached the warning level.
1 At least one of the error counters has reached the warning level.