Specifications

Interrupt Logic
10-33 CAN Controller Module
10.6.1 CAN Interrupt Flag Register (CAN_IFR)
The interrupt flag bits are set if the corresponding interrupt condition occurs.
The appropriate mailbox interrupt request is asserted only if the corresponding
interrupt mask in CAN_IMR register is set. The peripheral interrupt request
stays active until the interrupt flag is cleared by the CPU by writing a 1 to the
appropriate bit. An interrupt acknowledge does not clear the interrupt flags.
The MIFx flags cannot be cleared by writing to the IF register; instead, they
must be cleared by writing a 1 to the appropriate TA bit in the TCR register for
a transmit mailbox (mailboxes 2 to 5), or the RMP bit in the RCR register for
the receive mailbox (mailboxes 0 to 3). If another interrupt event associated
with the same interrupt request occurs before an earlier event has been
cleared, the interrupt request will continue to be asserted until after all interrupt
flags have been cleared.
Figure 10–21. CAN Interrupt Flag Register (CAN_IFR) — Address 7109h
15–14 13 12 11 10 9 8
Reserved MIF5 MIF4 MIF3 MIF2 MIF1 MIF0
R-0 R-0 R-0 R-0 R-0 R-0
76543210
Rsvd RMLIF AAIF WDIF WUIF BOIF EPIF WLIF
RC-0 RC-0 RC-0 RC-0 RC-0 RC-0 RC-0
Note: R = Read access; C = Clear; value following dash (–) = value after reset
Bits 15–14 Reserved.
Bits 13–8 MIFx. Mailbox Interrupt Flag (receive/transmit)
0 No message was transmitted or received.
1 The corresponding mailbox transmitted or received a message
successfully.
Each of the six mailboxes may initiate an interrupt. These interrupts can be a
receive or a transmit interrupt depending on the mailbox configuration. If one
of the configurable mailboxes is configured as Remote Request Mailbox (AAM
set) and a remote frame is received, a transmit interrupt is set after sending
the corresponding data frame. If a remote frame is sent, a receive interrupt is
set after the reception of the desired data frame.