Specifications

Interrupt Logic
10-32
10.6 Interrupt Logic
There are two interrupt requests from the CAN peripheral to the peripheral
interrupt expansion (PIE) controller, the mailbox interrupt and the error inter-
rupt. Both interrupts can assert either a high-priority request or a low-priority
request to the CPU. The following events may initiate an interrupt:
- Mailbox Interrupt
J A message was transmitted or received successfully. This event as-
serts the Mailbox interrupt.
- Abort Acknowledge Interrupt
J A send transmission was aborted. This event asserts the Error inter-
rupt.
- Write Denied Interrupt
J The CPU tried to write to a mailbox but was not allowed to. This event
asserts the Error interrupt.
- Wake-up Interrupt
J After wake-up, this interrupt is generated. This event asserts the Error
interrupt, even when clocks are not running.
- Receive Message Lost Interrupt
J An old message was overwritten by a new one. This event asserts the
Error interrupt.
- Bus Off Interrupt
J The CAN module enters the bus off state. This event asserts the Error
interrupt.
- Error Passive Interrupt
J The CAN module enters the error passive mode. This event asserts
the Error interrupt.
- Warning Level Interrupt
J One or both of the error counters is greater than or equal to 96. This
event asserts the Error interrupt.
Note: While servicing a CAN interrupt, the user should check all the bits in the
CAN_IFR register to ascertain if more than one bit has been set. The corre-
sponding ISRs should be executed for all the set bits. This must be done since
the core interrupt will be asserted only once, even if multiple bits are set in the
CAN_IFR register.