Specifications

Configuration Registers

2-3

System Configuration and Interrupts

2.2 Configuration Registers

2.2.1 System Control and Status Registers 1 and 2 (SCSR1, SCSR2)

Figure 2–2. System Control and Status Register 1 (SCSR1) — Address 07018h

15 14 13 12 11 10 9 8

OSC FAIL

FLAG

CLKSRC LPM1 LPM0 CLK_PS2 CLK_PS1 CLK_PS0

OSC FAIL

RESET

RW-0 RW-0 RW-0 RW-0 RW-1 RW-1 RW-1 RW-0

76543210

ADC

CLKEN

SCI

CLKEN

SPI

CLKEN

CAN

CLKEN

EVB

CLKEN

EVA

CLKEN

Reserved ILLADR

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 15 Oscillator Fail Flag

When set to 1, indicates that the external reference (oscillator or crystal) is op-

erating at a frequency too slow to be functional when compared to an internal

reference oscillator. Power on reset value is 0

0 Operating at too slow frequency

1 Operating normally.

Bit 14 CLKSRC. CLKOUT pin source select

0 CLKOUT pin has CPU Clock (30 MHz on a 30-MHz device) as the

output.

1 CLKOUT pin has Watchdog clock as the output

Bits 13–12 LPM(1:0). Low-power mode select

These bits indicate which low-power mode is entered when the CPU executes

the IDLE instruction. See Table 2–1 for description of the low-power modes.

Table 2–1. Description of Low-Power Modes

LPM(1:0) Low-Power mode selected

00 IDLE1 (LPM0)

01 IDLE2. (LPM1)

HALT (LPM2)