Specifications

Status Registers
10-31 CAN Controller Module
10.5.3 CAN Error Counter Register (CEC)
The CAN module contains two error counters: the receive error counter (REC)
and the transmit error counter (TEC). The values of both counters can be read
from the CEC register via the CPU interface.
Figure 10–20. CAN Error Counter Register (CEC) — Address 7108h
15–8
TEC[7:0]
R-0
7–0
REC[7:0]
R-0
Note: R = Read access; value following dash (–) = value after reset
After exceeding the error passive limit (128), REC is not increased any further.
When a message is received correctly, the counter is set again to a value be-
tween 119 and 127. After reaching the bus-off status, TEC is undefined, while
REC is cleared and its function is changed: It will be incremented after every
11 consecutive recessive bits on the bus. These 11 bits correspond to the gap
between two telegrams on the bus. If the receive counter reaches 128, the
module changes automatically back to the status bus-on if bit ABO in MCR is
set. Otherwise, it changes when the recovery sequence of 11 × 128 bits has
finished and the CCR bit in the MCR register is reset by the DSP. All internal
flags are reset and the error counters are cleared. The configuration registers
keep the programmed values.
After the power-down mode, the error counters stay unchanged. They are
cleared when entering the configuration mode.