Specifications

Status Registers
10-29 CAN Controller Module
Bit 2 Reserved.
Bit 1 RM. The CAN module is in the Receive Mode.
This bit reflects what the CBM is actually doing regardless of mailbox configu-
ration.
0 The CAN core module is not receiving a message.
1 The CAN core module is receiving a message.
Bit 0 TM. The CAN module is in the Transmit Mode.
This bit reflects what the CBM is actually doing regardless of mailbox configu-
ration.
0 The CAN core module is not transmitting a message.
1 The CAN core module is transmitting a message.
10.5.2 Error Status Register (ESR)
The error status register (see Figure 10–19) is used to display errors that oc-
curred during operation. Only the first error is stored. Subsequent errors do not
change the status of the register. These registers are cleared by writing a 1 to
them except for the SA1 flag, which is cleared by any recessive bit on the bus.
Bits 8 to 3 are error bits that can be read and cleared by writing a 1 to them.
Bits 2 to 0 are status bits that cannot be cleared, only read.
Figure 10–19. Error Status Register (ESR) — Address 7106h
15–9 8
Reserved FER
RC-0
76543210
BEF
SA1 CRCE SER ACKE BO EP EW
RC-0 RC-1 RC-0 RC-0 RC-0 R-0 R-0 R-0
Note: R = Read access; C = Clear; value following dash (–) = value after reset
Bits 15–9 Reserved.
Bit 8 FER. Form Error Flag
0 The CAN module was able to send and receive correctly.
1 A Form Error occurred on the bus. This means that one or more of the
fixed-form bit fields had the wrong level on the bus.